1. Technical Field
The present application relates generally to an improved data processing system and method. More specifically, the present application is directed to a system and method for modifying a test pattern so as to control power supply noise during testing of an integrated circuit device. In particular, the system and method of the illustrative embodiments set forth hereafter are directed to controlling power supply noise during testing so as to provide a more accurate determination of a minimum functional voltage of an integrated circuit device when compared to known techniques.
2. Description of Related Art
Testing of integrated circuit devices is an important factor in ensuring proper functionality of the integrated circuit devices as well as for determining the functional capabilities of the integrated circuit devices for categorization purposes, e.g., binning. As integrated circuit devices have become more complex, in an effort to reduce the complexity and cost of the external testing equipment, testing of the integrated circuit devices has moved from the exclusive use of external testing equipment to greater dependence on built-in-self-test (BIST) circuitry provided on the integrated circuit device itself. Such BIST circuitry may be used to test the functional logic of the integrated circuit device, i.e. LBIST, arrays of the integrated circuit device, i.e. ABIST, or the like.
Typically, with LBIST circuitry provided on the integrated circuit device, a test pattern generator generates a test pattern that is applied to the functional logic of the integrated circuit device, or circuit under test (CUT), which in turn outputs a response to a response analyzer that generates a signature based on the analyzed response. With LBIST, all of the logic on the integrated circuit device is tested using a large number of test patterns to ensure a high test coverage. The resultant data generated by the logic of the integrated circuit device is captured in “strings” of output latches of the integrated circuit device. This data is combined to form one signature which depends on values of all the individual latch bits. This signature is updated after each test so that, in the end, the final signature depends on the values of all the latch bits as determined after all tests.
The correct signature can be determined by simply running the tests at low frequency where all of the logic is expected to operate correctly. The test signature generated from this low frequency testing is referred to as the “golden signature.” This golden signature is then used to compare against signatures obtained as the test frequency is increased. The integrated circuit device is typically divided up into many different scan “strings” with each one having its own golden signature and subsequent test signatures.
By performing such testing of the functional logic of an integrated circuit device using LBIST, various operational characteristics of the integrated circuit device may be calculated. One such operational characteristic is the minimum functional voltage of the integrated circuit device, i.e. Vminf. A problem arises, however, when using LBIST to determine Vminf in that the integrated circuit device does not operate in an idealized manner in which the voltage inside the integrated circuit device, i.e. the on-chip voltage Vdd, is at a constant voltage at all times. To the contrary, the on-chip voltage Vdd is a complex function involving characteristics of the power supply (e.g., resistance, capacitance, inductance at the chip, package, and board levels, etc.) and the current-vs-voltage characteristics of the circuits on the chip, i.e. in the integrated circuit device.
One reason why the integrated circuit device does not operate in an idealized manner is that the execution of the test patterns in the functional logic is controlled by an LBIST controller which controls various signal switching events for specifying the operational state of the functional logic for each functional cycle. The various signal switching events used to control the operational state of the functional logic for each cycle during the LBIST result in various current draws from the on-chip capacitance and from higher levels of the power supply (e.g., package, board, voltage regulator, etc.).
Short term excess of current demand over average will reduce the voltage in the on-chip capacitance. Short term current demand which is less than average will result in increased charge stored in the on-chip capacitance. Thus, as the states of the LBIST change, the voltage in the on-chip capacitance changes thereby possibly causing droops in the on-chip voltage Vdd. Such changes in the on-chip voltage Vdd from an idealized constant voltage is referred to as power supply noise. If the on-chip voltage Vdd droops too far, i.e. the power supply noise is too great, the corresponding test may fail.
Thus, depending upon the sequence of states used for the particular tests, certain tests may fail at different external voltages from the voltage supply. Since such tests may be used to determine Vminf, these tests may indicate a Vminf that is greater than is actually required due to the failure of certain tests. Thus, there is an uncertainty in the determination of the Vminf calculated using such LBIST in the known technology.